1. Field of the Invention
The invention generally relates to memory devices and, more particularly, to reading a special mode register of a memory device.
2. Description of the Related Art
In addition to storing and retrieving data, modern memory devices typically provide information and controls which may be used to access information about the memory device and to adjust the operational characteristics of the memory device. The information and controls are usually accessible through registers in the memory device known as mode registers. Because the memory device may contain more information and controls than are accessible by a single mode register (MR), the memory device may contain another mode register, known as the extended mode register (EMR), to access the remaining information and controls.
Each mode register is typically accessed using what is commonly referred to as a mode register set command (MRS command). The MRS command may be used to change control bits in the accessed mode register, which may change how the device operates. The control bits may also be used to access information about the device. The information about the device, such as a vendor ID (information identifying a manufacturer of the device) or operational characteristics of the device (such as temperature), may be stored in other registers known as special mode registers (SMR). Use of the control bits of an EMR to control the device and to access the special mode registers is described below with respect to FIGS. 1A-B.
The control bits 100 of EMR are depicted in FIG. 1A. Bank address bits (BA[1:0]) 102 provided with the MRS command are used to choose between MR (where BA[1:0]=‘00’) and EMR (where BA[1:0]=‘01’). Other bank address combinations in the prior art (BA[1:0]=‘10’ and BA[1:0]=‘11’) may be reserved for future use (RFU). In the case depicted in FIG. 1, EMR (BA[1:0]=‘01’) is being accessed by the MRS command.
The address bits (A[11:0]) 110 are used to set the control bits in EMR as follows. Bits A[1:0] may set an output drive impedance (Data Z) for the device, bits A[3:2] may set an on-die termination resistance (Rt), bits A[5:4] may set a number of write recovery cycles (WR), bit A6 may control a delay-locked loop (DLL), and bit A11 may be used to place the device in a low power mode (LP). Other bits, A[9:7], may be reserved for future use (RFU). Bit A10 may be used to access a special mode register containing vendor ID information (V),
FIG. 1B is a timing diagram which depicts the prior art method for reading the vendor ID. In order to read a vendor ID of the prior art the special mode register for the vendor ID is first placed in a read mode by setting bit A10 in the EMR using the MRS command. Thus, at time T1, the MRS command is issued, EMR is selected by setting BA[1:0 ]=‘01’, and bit A10 is asserted to indicate that the vendor ID information is to be read. The command may also set other bits in EMR using the remaining address bits A[9:0 ] and A11. Thus, each time the vendor ID is read, other control bits are set at the same time. At some time later, after the vendor ID is placed in read mode, the vendor ID information 120 (containing a vendor code and revision ID) is output on a data bus (such as a 16 bit data bus, DQ[15:0 ]).
While the vendor ID is in read mode, the vendor ID information 120 continues to be output on the data bus. In order take the vendor ID out of read mode (and to stop driving the vendor ID information 120 onto the data bus), another MRS command must be issued with A10 at a low logic level, thus clearing the vendor ID bit in EMR. Accordingly, at T2, another MRS command may be issued with BA[1:0]=‘01’, thus selecting EMR as the destination register, and bit A10 driven to a low logic level, thus clearing the vendor ID bit in EMR. At some time T3 after the vendor ID bit in EMR is cleared, the device will stop driving the vendor ID information onto the data bus, and the data bus may subsequently be used to read other data or to input data into the memory device.
Such a method of reading a special mode register in a memory device has several drawbacks. First, in order to read the special mode register, two commands are required, one to place the special mode register in read mode and another to take the special mode register out of read mode. Each of these commands takes a number of clock cycles to execute. Also, if the user of the device inadvertently places the special mode register into read mode by issuing an MRS command for EMR with A10=‘1’, or if the user intentionally places the special mode register in read mode but neglects to later take the special mode register out of read mode, the special mode register data will continue to be driven onto the data bus. If the user later tries to write to the memory device and drives data onto the bus while the special mode register information is being driven onto the bus, the data bus is placed in contention.
Accordingly, what is needed is an improved method for reading a special mode register.